Having nailed the delay code I've spent most of the evening reading up on the SX52 memory architecture and the PAL timing signal. To start with I've created the signal needed for each scanline (see previous blog with timing diagram)
The first attempt didn't go too well
It was only a few minutes though before I realise my timing was out by a few clock cycles. The reason? Well in order to generate say the SYNC pulse 0.0V on RE port for 4.7µs we need to delay for 4.7µs*1000/12.5ns = 376 clock cycles, so I did the following
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mov RE, VID_SYNC
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DELAY(376)
The problem though is that really we've taken up 378 clock cycles and thus the code is executing for 25ns longer than we need it to. Couple this with all the other mov/delay statements for the other parts of the signal and we end up many cycles out of sync. The solution is simple, a mov takes 1 cycle or in the case of a compound mov (which this is) 2 cycles, so we just reduce the delay by 2 cycles to give
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mov RE, VID_SYNC ; 2
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DELAY(376-2) ; 376-2
The result is a lot more promising, using VID_WHITE (1.0v) for the output port RE gives us a nice white screen, however we're not finished yet, since there is not handling of the vertical sync yet.
So thats as far as I managed to get by the end of Saturday. I expected to have a good few hours sunday to work on getting the vsync sorted and plotting a specific pixel, but plans change. If I'm lucky I'll squeeze in a few more hours tonight and hopefully finish things off.
